Data acquisition technology have been widely applied to various fields, such as electronic measurement, communication, radar, aerospace and industry. With the development of technology and engineering application, the complexity of application system increases, and the frequency of the signal under acquisition (a continuous-time and continuous-amplitude analog signal, also called as input signal of DAS) is much higher than ever, that demands data acquisition system to raise its sampling rate. However, subject to the performance of analog-to-digital converter (ADC), it is rather difficult to dramatically enhance the real-time sampling rate of data acquisition system (DAS) to acquire enough waveform information of the signal under acquisition, some waveform information of the signal under acquisition will be lost, leading to the distortion of reconstructed signal. To solve the problem of the distortion of reconstructed signal, random sampling is employed to obtain ultrahigh sampling rate waveform information of periodic signal through multiple sampling.
Random sampling, belonging to non-real-time sampling, is an equivalent sampling, which uses the randomness of sampling signal relative to the signal under acquisition and triggering event to obtain high sampling rate through multiple acquisition and data merging. In practice, considering the randomness of the time interval between the trigger time and the first sampling time after the trigger, Random sampling uses high precise time interval measurement to obtain the time interval, and then reconstruct the original signal i.e. the signal under acquisition with higher sampling rate on basis of the time interval of each acquisition. The process of acquiring, storing and reconstructing of the signal under acquisition is shown in FIG. 1.
As shown in FIG. 1, random sampling employs sampling clock of period Ts (sampling rate of ADC) to acquire the sampled data of the signal under acquisition multiple times (supposing the number of acquisition times is N), and multiple pluralities of sampled data dij do are obtained, then stored in acquisition normal sequence (acquisition storage). Wherein, i is acquisition serial number and j is the sampled data sequence number. After the acquisition storage, there is reconstruction storage, the ith storage of sampled data is based on the time interval ti between trigger time Tri of the ith acquisition and the first sampling time after the trigger of the ith acquisition. The waveform of the original signal, i.e. the signal under acquisition will be reconstructed with sampled data of the reconstruction storage (waveform reconstruction).
Given the measurement resolution is Ts/M, equivalent sampling rate of reconstructed waveform is M times original sample rate, i.e. M/Ts. That makes the data acquisition system having much higher equivalent sampling rate, and the equivalent sampling rate is irrelevant to the sampling rate of ADC, but concerned only to the measurement accuracy of time interval ti, the higher equivalent sampling rate depends on the higher measurement accuracy of time interval ti.
FIG. 2 is a functional block diagram of the random sampling system in prior art.
The conventional random sampling is realized on the basis of analog circuits and logic devices. As shown in FIG. 2, the conventional random sampling system comprises signal conditioning circuit, analog trigger channel, analog-to-digital converter (ADC), field programmable gate array (FPGA), digital signal processor (DSP), sampling clock generator, time interval measurement module, etc.
After conditioned by signal conditioning circuit, the signal under acquisition is sampled and quantized by ADC, and then the sampled data SDATA and synchronous clock DCLK is sent to FPGA. At the same time, the trigger is also sent from analog trigger channel to the FPGA. Every time when acquisition begins, the FPGA opens the writing enable wen to store a section (pre-triggering depth) of pre-triggering sampled data to the FIFO of FPGA, then opens reading enable ren to maintain the volume of pre-triggering sampled data with pre-triggering depth, waiting for triggering event. When the triggering event (e.g. rising or falling edge of the signal under acquisition) comes, the analog trigger channel sends a trigger signal to FPGA, and then FPGA closes reading enable ren, and generates a measurement pulse based on the time interval ti between trigger time Tri of the ith acquisition and the first sampling time after the trigger of the ith acquisition. The measurement pulse is sent to the time interval measurement module for measuring. When the FIFO of FPGA attains sampled data up to the volume required, an acquisition is accomplished. FPGA closes writing enable wen, and calculates the corresponding address of the plurality of sampled data for back-end waveform display according to the result of time interval of the acquisition. The process of acquisition and time interval measurement is repeated multiple times, and multiple pluralities of sampled data are obtained. Each plurality of sampled data is stored according to the calculated corresponding address. The waveform reconstruction of data acquisition is realized based on stored sampled data. Considering the frequency irrelevance of the sampling clock and the signal under acquisition, the sampled data in FIFO can cover all locations after some time. As shown in lower part of FIG. 1, the signal under acquisition is completely reconstructed when displayed. The processes mentioned above are regulated by digital signal processor (DSP).
The aforementioned random sampling can solve the problem of high-frequency signal acquisition that cannot meet the Nyquist sampling theorem, but its hardware circuit is rather complicated. With regard to the signal under acquisition, which frequency is relatively not much higher comparing to the sampling clock, but required more specific waveform details, the random sampling mentioned above is dispensable.